The Gm/id Methodology, A Sizing Tool For Low-voltage Analog Cmos Circuits
by Paul Jespers(Author)
Reviews: 5.0
(5 reviews)
Formats
Hardback/English
USD 150.00
Description
IC designers appraise currently MOS transistor geometries and currents to compromise objectives like gain-bandwidth, slew-rate, dynamic range, noise, non-linear distortion, etc. Making optimal choices is a difficult task. How to minimize for instance the power consumption of an operational amplifier without too much penalty regarding area while keeping the gain-bandwidth unaffected in the same time? Moderate inversion yields high gains, but the concomitant area increase adds parasitics that rest
